1. Field of the Invention
The present invention relates generally to handling of sensitive electrical equipment, and particularly to the proper handling of electronic devices at the wafer level, which are sensitive to electrostatic discharge (ESD) events.
2. Background of the Invention
The need for higher recording densities and wider bandwidth within the storage industry has been achieved by producing heads with thinner gap thicknesses, narrower track widths and the evolution of novel MR (magneto-resistive) and GMR (giant magneto-resistive) materials. This natural progression to smaller/thinner dimensions in a magneto-resistive head build-up has lead to the increased sensitivity at the wafer level to ESD events, which can destroy the device.
As semiconductor processing advances and devices grow smaller, the operational bias currents necessary to operate such devices decreases as well. This typically results in devices that are more sensitive to uncontrolled current flow, particularly spikes of high current.
For example, a typical MR head is built-up on an ceramic substrate like AlTiC (Aluminum Oxide Titanium Carbide). The head itself is comprised of both insulating and conducting layers that together can act as a capacitive device by storing and discharging potential. As the wafers are processed (handled) through the fabrication plant their insulated conductor properties allow themselves to become “tribocharged” when they come in contact with other insulating objects, such as those made with Teflon, PVC or non-dissipative plastic. Current vacuum wand tips are made from just such insulating materials and cannot be grounded. The act of charge exchange between two objects via friction is called tribocharging, which occurs when one object donates electrons and becomes positively charged and the other accepts electrons and becomes negatively charged.
It has been demonstrated that tribocharging with insulating materials can result in potentials of 20 kV on a wafer surface. Once a charged wafer comes in contact with a hard ground, such as a grounded conductor with relatively low resistance, the resulting “spike” in current flow as the wafer discharges itself can result in device failure. This ESD event results in typical yield losses of 10-20% per wafer and as high as 40-50% per wafer.
Thus, as wafers move through the fabrication process, they are constantly being handled—i.e. charged and discharged. Since all wafer handling cannot be eliminated from the wafer line, the typical fabrication setup would benefit from a way to safely discharge the wafers during handling and prior to contact with earth ground.